• DocumentCode
    3320191
  • Title

    Functional Refinement: A Generic Methodology for Managing ESL Abstractions

  • Author

    Abrar, Syed Saif ; Thimmapuram, Aravinda

  • Author_Institution
    NXP Semicond., India
  • fYear
    2010
  • fDate
    3-7 Jan. 2010
  • Firstpage
    122
  • Lastpage
    127
  • Abstract
    Ever increasing complexity of SoCs has resulted in starting the system design at a higher level of abstraction. System-level design methodology envisages step-wise refinement of high-level models towards final RTL. However, current practices are limited to only interface-refinement and the true functionality refinement is performed by developing a different model for each abstraction-level. This results in minimal re-use of existing model, loss of efforts and high maintenance cost of multiple models. This paper presents a novel methodology that enables seamless refinement of IP model functionality from one level to another. The presented methodology is generic to be applied to various SoC design tasks. This paper demonstrates the application of the methodology to software energy-estimation for a DSP and functional-cum-timing refinement of DDR-memory model. The proposed methodology resulted in complete re-use of the existing models, easy availability of various model-abstractions and 20% savings in development-effort of a new model.
  • Keywords
    digital signal processing chips; instruction sets; integrated circuit design; memory architecture; system-on-chip; DDR-memory model; DSP; ESL abstraction; IP model functionality; SoC complexity; SoC design; functional refinement; instruction set simulator; model abstraction; software energy-estimation; system-level design; Application software; Availability; Concrete; Conference management; Costs; Digital signal processing; Programming; System-level design; Timing; Very large scale integration; ESL; functional; high-level; refinement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2010. VLSID '10. 23rd International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4244-5541-6
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2010.26
  • Filename
    5401265