Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

Author

Dutta, R. ; Bhattacharyya, T.K. ; Gao, X. ; Klumperink, E.A.M.

Author_Institution

E & ECE Dept., IIT Kharagpur, Kharagpur, India

fYear

2010

fDate

3-7 Jan. 2010

Firstpage

152

Lastpage

157

Abstract

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.

Keywords

CMOS logic circuits; circuit optimisation; delays; integrated circuit design; jitter; logic design; low-power electronics; jitter variance; large load capacitances; low power low mismatch jitter buffers; minimum delay; minimum power-delay product; multi phase clock generation circuits; optimum stage ratio; power dissipation; size 180 nm; size 90 nm; tapered CMOS inverter; Analytical models; CMOS technology; Capacitance; Circuit simulation; Clocks; Delay; Inverters; Jitter; Power dissipation; Power generation; CMOS inverter; figure of merit; low power; mismatch jitter; multiphase clock; stage ratio; tapering factor;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2010. VLSID '10. 23rd International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

978-1-4244-5541-6

Type

conf

DOI

10.1109/VLSI.Design.2010.78

Filename

5401276