DocumentCode
3320774
Title
cHPP controller: A High Performance Hyper-node Hardware Accelerator
Author
Yong Su ; Feilong Liu ; Zheng Cao ; Zhan Wang ; Xiaoli Liu ; Xuejun An ; Ninghui Sun
Author_Institution
Nat. Res. Center for Intell. Comput. Syst., Inst. of Comput. Technol., Beijing, China
fYear
2013
fDate
16-18 Dec. 2013
Firstpage
117
Lastpage
123
Abstract
The high-density blade server provides an attractive solution for the rapid increasing demand on computing. The degree of parallelism inside a blade enclosure nowadays has reach up to hundreds of cores. In such parallelism, it is necessary to accelerate communications inside a blade enclosure. However, commercial products seldom set foot in the optimization based on hardware. A hyper-node controller is proposed to provide a low overhead and high performance interconnection based on PCIe, which supports global address space, user-level communication, and efficient communication primitives. Furthermore, the efficient sharing of I/O resource is another goal of this design. The prototype of the hyper-node controller is implemented in FPGA. The testing results show the lowest latency is only 1.242us and the highest bandwidth is 3.19GB/s, which is almost 99.7% of the theoretic peak bandwidth.
Keywords
field programmable gate arrays; parallel processing; resource allocation; system buses; FPGA; I/O resource sharing; PCIe; cHPP controller; communication primitives; global address space; high performance hyper-node hardware accelerator; hypernode controller; latency; user-level communication; Bandwidth; Blades; Engines; Hardware; Payloads; Protocols; Virtualization; blade server; direct memory access; hyper-node controller; input output virtualization; large scale distributed computing system;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Computing, Applications and Technologies (PDCAT), 2013 International Conference on
Conference_Location
Taipei
Print_ISBN
978-1-4799-2418-9
Type
conf
DOI
10.1109/PDCAT.2013.25
Filename
6904242
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