An efficient max-log MAP algorithm for VLSI implementation of turbo decoders

Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting in a large area overhead, a big drawback. The scaled Max-log MAP algorithm is a common approach to implement the MAP algorithm due to its efficient architecture with its acceptable performance. Although many works have been reported to reduce the area of the MAP unit, an efficient VLSI architecture with minimum silicon area is still missing. To address this challenge, in this paper, a novel method based on a novel form of computation is introduced, removing a single bit from computations of the max-log MAP algorithm compared to the conventional architectures. The proposed method can be applied to any max-log MAP architecture reported to-date.