High Speed Serial Link Transmitter for 10Gig Ethernet Applications

Author

Ramamoorthy, Navin K. ; Jayabharath, R.M. ; Muniyappa, Vishwanath

Author_Institution

Syst. & Tech., Group, IBM India Pvt., Ltd., India

fYear

2010

fDate

3-7 Jan. 2010

Firstpage

246

Lastpage

251

Abstract

This paper presents a Current Mode Logic (CML) transmitter circuit that forms part of a Serializer/ Deserializer IP core used in a high speed I/O links targeted for 10+ Gbps Ethernet applications. The paper discusses the 3 tap FIR filter equalization implemented to minimize the effects of Inter Symbol interference (ISI) and attenuation of high speed signal content in the channel. The paper also discusses on the design optimization implemented using hybrid segmentation of driver segments which results in improved control on the step sizes variations, Differential Non Linearity (DNL) errors at segment boundaries over Process mismatch variations.

Keywords

FIR filters; IP networks; equalisers; interference suppression; intersymbol interference; local area networks; transmitters; 3 tap FIR filter equalization; Ethernet; ISI; current mode logic; deserializer IP core; design optimization; differential nonlinearity errors; high speed I/O links; high speed serial link transmitter; high speed signal attenuation; intersymbol interference; process mismatch variations; serializer IP core; transmitter circuit; Attenuation; Design optimization; Error correction; Ethernet networks; Finite impulse response filter; Intersymbol interference; Linearity; Logic circuits; Size control; Transmitters; CML; Equalization; Gigabits per second(Gbps); ISI; SerDes I/O; Transmitter; tap co-efficients;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2010. VLSID '10. 23rd International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

978-1-4244-5541-6

Type

conf

DOI

10.1109/VLSI.Design.2010.51

Filename

5401323