DocumentCode :
3321322
Title :
A Reconfigurable Architecture for Secure Multimedia Delivery
Author :
Pande, Amit ; Zambreno, Joseph
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear :
2010
fDate :
3-7 Jan. 2010
Firstpage :
258
Lastpage :
263
Abstract :
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the discrete wavelet transform (DWT). This parameterized construction promises multimedia encryption and is also well-suited to a hardware implementation due to our derivation of rational filter coefficients. We achieve an efficient and high-throughput reconfigurable hardware implementation through the use of LUT-based constant multipliers enabling run-time reconfiguration of encryption key. We also compare our prototype (using a Xilinx Virtex 4 FPGA) to several existing implementations in the research literature and show that we achieve superior performance as compared to both traditional CPU-based and custom VLSI approaches while adding features for secure multimedia delivery.
Keywords :
VLSI; cryptography; discrete wavelet transforms; multimedia communication; real-time systems; reconfigurable architectures; LUT-based constant multipliers; VLSI; Xilinx Virtex 4 FPGA; discrete wavelet transform; encryption key; multimedia encryption; real-time video delivery; reconfigurable architecture; secure multimedia delivery; Cryptography; Discrete wavelet transforms; Field programmable gate arrays; Filter bank; Hardware; Image coding; Low pass filters; Multimedia systems; Reconfigurable architectures; Security;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
978-1-4244-5541-6
Type :
conf
DOI :
10.1109/VLSI.Design.2010.50
Filename :
5401325
Link To Document :
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