Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link

To achieve high speed data signaling rates with the internal fast clock operating at half its speed,the XDR (extreme data rate) I/O link employs dual-edge signaling where in data bits are transmitted on both the edges (rise/fall) of transmit clock. Duty cycle correction technique is used to provide high frequency low jitter clocks that have 50% duty cycle. This paper compares two different techniques to implement duty cycle corrector (DCC). These techniques are implemented in high speed I/O operating at data rate of 4Gbps and 6.4Gbps in TSMC 65nm & TSMC 40nm technology achieving an output duty cycle error below ±2% for ±10% input duty cycle error.