DocumentCode
3321481
Title
Impact of back side defects on feol processes and yield
Author
Pressley, Laura ; Hardin, Shirley ; Harper, Kevin ; Dunham, Brian ; Sutton, Dan ; Kirsch, Travis ; Allen, Mike ; Klingemann, Buster ; Mathews, Teresa ; Kohler, Laurence ; Lansford, Chris ; Couteau, Terri ; Hance, Bryon ; Darilek, John ; Cariss, Carolyn ;
Author_Institution
Fab25, Spansion LLC, Austin, TX
fYear
2005
fDate
11-12 April 2005
Firstpage
32
Lastpage
37
Abstract
Front end-of-line (FEOL) front side and back side defect investigations revealed a previously unknown back side defect mechanism that may negatively affected die sort yields. Using the AMAT SEMVisiontrade and Compasstrade tools, the KLA-Tencor AITtrade and SP1 BSIMtrade tools, and the JEOL SEMtrade, a detailed FEOL front side and back side defect partition showed that several defect mechanisms were operating in the FEOL and a previously unknown back side defect mechanism was newly identified. These new defects were large gauge/scratch type defects greater than 100 mum and were found, prior to processing in our facility, on every incoming silicon wafer from several silicon substrate suppliers. The new back side defect data enabled the Si suppliers to identify the root cause to be a marginal furnace anneal process and marginal boat configuration at their various manufacturing sites. This FEOL back side defect characterization revealed a previously unknown defect mechanism that affected every production starting Si wafer from those suppliers and corrective actions are in place at each supplier sites to reduce and eliminate them
Keywords
annealing; elemental semiconductors; furnaces; inspection; integrated circuit yield; production facilities; AMAT SEMVision; Compass; FEOL processes; JEOL SEM; KLA-Tencor AIT; SP1 BSIM; Si; back side defects; front end-of-line back side defect; front end-of-line front side defect; marginal boat configuration; marginal furnace anneal process; silicon substrate suppliers; silicon wafer; Annealing; Boats; Furnaces; Manufacturing processes; Production; Scanning electron microscopy; Semiconductor devices; Silicon; Substrates; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI
Conference_Location
Munich
Print_ISBN
0-7803-8997-2
Type
conf
DOI
10.1109/ASMC.2005.1438763
Filename
1438763
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