An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters

This paper presents a fast, accurate and robust method for bottom-up extraction of analog behavioral model parameters from the corresponding transistor level netlists. The proposed Verilog-A in-loop simulation based modeling approach is generic and can estimate the parameters of the corresponding model of any given circuit using relevant test-benches, thus removing the need to implement structure based estimation tools for each circuit. The models are usually non-linear with respect to the parameters and often the optimization problem becomes nonconvex. A hybrid method based on co-operation and switching between search and gradient methods is proposed for achieving significantly faster convergence to the global minima even in presence of local minima in such non-convex cases. This method is applied by the authors to a wide variety of analog circuits, and is demonstrated in the paper using two distinctly different analog circuits. Simulation results comparing the model and transistor level netlist show that high level of accuracy can be achieved. The comparison of the search, gradient and the proposed hybrid method is presented.