• DocumentCode
    3321547
  • Title

    Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2010
  • fDate
    3-7 Jan. 2010
  • Firstpage
    39
  • Lastpage
    44
  • Abstract
    Bridging and interconnect open faults are defined using subsets of lines. We study the possibility of identifying input vectors that are effective as test vectors for such faults without enumerating the faults. This process does not require accurate layout information, it can handle very large numbers of faults, and it deals with undetectable faults implicitly. We describe a static test compaction process that uses the ability to identify effective test vectors without enumerating faults. This process selects a subset T of a given test set U such that T is guaranteed to detect the same faults as U. We also describe a test generation process based on the same concept. Finally, we show how this concept can be used to compare test sets.
  • Keywords
    circuit testing; fault diagnosis; logic circuits; logic testing; set theory; fault enumeration; layout information; line subset; logic fault models; open fault interconnection; static test compaction process; test generation process; Bridge circuits; Capacitance; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Integrated circuit interconnections; Leakage current; Logic testing; bridging faults; interconnect open faults; static test compaction; test generation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2010. VLSID '10. 23rd International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4244-5541-6
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2010.16
  • Filename
    5401335