4 GHz 130nm Low Voltage PLL Based on Self Biased Technique

This paper explores a PLL core design that can satisfy a wide range of high frequency serial data communication applications. There exist several high frequency serial data communication protocols that co-exist today. The PLL design requirements for all these clock frequencies separately call for enormous design effort in terms of time and cost. It is desired to design a PLL core which makes it possible to address a wide segment of clock frequency requirement. The PLL achieves this using single 1.2 V supply, it doesn´t use any special mask layers and also doesn´t need a bandgap reference for its operation. This PLL is based on self-biased technique and achieves high process technology independence, fixed damping factor, fixed bandwidth to operating frequency range and input phase offset cancellation. Here the self biased PLL in 130 nm CMOS technology achieves the frequency range of 400 MHz to 4 GHz. The PLL core is designed to accept a wide range of input reference frequencies.