DocumentCode :
3321996
Title :
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance
Author :
Leary, Glenn ; Chatha, Karam S.
Author_Institution :
Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
fYear :
2010
fDate :
3-7 Jan. 2010
Firstpage :
200
Lastpage :
205
Abstract :
Many SoC architectures aimed at the multimedia domain support multiple use cases where only a subset of the applications is active at any time. Further, each multimedia application itself poses strict constraints on core-to-core communication latency. This paper presents an approach for automated synthesis of NoC architectures for such an SoC. We evaluated our design approach through comparisons with two existing techniques aimed at generating best effort and guaranteed throughput designs. Designs generated by our approach showed a marked improvement in both power consumption (12.3% decrease) and resource requirements (12.9% decrease) in comparison to the best effort NoC design approach. In comparison to the existing guaranteed throughput design approach our designs can guarantee core-to-core latency while consuming less power (8.1% decrease) and resources (7.9% decrease).
Keywords :
integrated circuit design; network-on-chip; NoC architectures; SoC architectures; automated synthesis; core-to-core communication latency; network-on-chip; system-on-chips; Bandwidth; Delay; Design methodology; Displays; Multimedia systems; Network-on-a-chip; Throughput; Upper bound; Video recording; Wireless communication; Network-on-chip; synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
978-1-4244-5541-6
Type :
conf
DOI :
10.1109/VLSI.Design.2010.73
Filename :
5401355
Link To Document :
بازگشت