An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology

This paper presents ways to improve accuracy of performance prediction for geometric program based analog design in submicron regime. Geometric program requires a special monomial form of the device model it uses. The major sources of inaccuracy in this basic model have been identified and it has been shown that slightly relaxing the strict monomial form in order to include second order effects can greatly improve the accuracy. In order to make use of this model we deploy it in collaboration with an iterative solution betterment scheme, by solving the sizing problem as a sequence of geometric programs instead of a single one. We illustrate the efficacy of our scheme through a folded-cascode op-amp sizing example.