Title :
A Unified Solution to Scan Test Volume, Time, and Power Minimization
Author :
Chen, Zhen ; Seth, Sharad ; Xiang, Dong ; Bhattacharya, Bhargab B.
Author_Institution :
Dept. of Comp. Sci. & Techn., Tsinghua Univ., Beijing, China
Abstract :
The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures.
Keywords :
circuit testing; embedded systems; flip-flops; logic testing; double-tree scan-path architecture; external testing; test data reduction; test power minimization; test time reduction; Automatic test pattern generation; Broadcasting; Circuit testing; Computer science; Costs; Data engineering; Life testing; Power engineering and energy; Software testing; Very large scale integration; Nonlinear scan; Test data reduction; Test power minimization; Test time reduction;
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-5541-6
DOI :
10.1109/VLSI.Design.2010.44
