DocumentCode
3322231
Title
Designing efficient elliptic Curve Diffie-Hellman accelerators for embedded systems
Author
Fournaris, Apostolos P. ; Zafeirakis, Ioannis ; Koulamas, Christos ; Sklavos, Nicolas ; Koufopavlou, Odysseas
Author_Institution
Ind. Syst. Inst. (ISI) / R.C.“ATHENA”, Patra, Greece
fYear
2015
fDate
24-27 May 2015
Firstpage
2025
Lastpage
2028
Abstract
In this paper, a methodology towards a hardware/software implementation of an Elliptic Curve Diffie Hellman (ECDH) scheme is proposed in an effort to overcome the design problems of Elliptic Curve Cryptography (ECC) systems stemming from the highly constrained embedded system hardware and software environment (restricted RAM, storage and processing power). To achieve that, instead of the excessively slow software ECDH implementations or monolithic, not flexible hardware implementations, we propose the use of a flexible, scalar multiplication (SM) accelerator connected to the main embedded system processor in order to speed up ECDH functionality without downgrading the overall main processor performance. The proposed solution can be used for a wide variety of GF(2k) based Elliptic Curves (EC) and is capable of shifting from one EC to another EC at runtime (flexibility). The proposed architecture was implemented and tested in Xilinx Virtex 5 technology by realizing the proposed SM accelerator unit interconnected with a Xilinx microblaze softcore processor.
Keywords
embedded systems; integrated circuit design; microprocessor chips; monolithic integrated circuits; public key cryptography; random-access storage; ECC systems; ECDH functionality; ECDH scheme; SM accelerator; Xilinx Virtex 5 technology; Xilinx microblaze softcore processor; elliptic curve Diffie-Hellman accelerators; elliptic curve cryptography; embedded system hardware; embedded system processor; embedded systems; monolithic implementations; restricted RAM; scalar multiplication; software ECDH implementations; Computer architecture; Delays; Elliptic curve cryptography; Embedded systems; Hardware; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7169074
Filename
7169074
Link To Document