Test generation at the transistor level for MOS VLSI combinational logic circuits

An extension of the existing method of generating tests at the logical gate level is introduced to generate test patterns for MOS digital circuits at the transistor level. The CPTGTL (critical path test generation at the transistor level) uses sensitized paths throughout the wGS (wired gate switch) network to detect faults. The CPTGTL uses stuck switch faults to generate tests. A faulty switch in the wGS networks is either permanently stuck open or permanently stuck short. To identify a faulty switch along a sensitized path in the wGS implementation of MOS circuits, additional logic values, high-zero-impedance and high-one-impedance (critical high-impedance), have been defined