Realities of Multi-Core CPU Chips and Memory Contention

The relationship between the CPU and memory has always been of prime importance in the HPC ecosphere. Current trends in multi-core chip designs look to alarmingly upset the balance of that relationship. The number of CPUs in a chip is growing, while the interface to memory stays relatively static. How are we to adapt our software to this new paradigm in order to maximize the utility of those extra CPUs? The answer, of course, depends on your code. We show an example of some simple tools and metrics that identify the points in a parallel application where the memory resource is over-stressed. Surprisingly, in our sample application, these points are not necessarily the most time-consuming ones in the case of a non-multi-core version. Careful removal of some parallel regions shows the potential for improved scalability on multi-core systems, as the benefit of the multi-core portions of the code outweigh the relatively small areas where parallelism is now removed. Application of this technique should be broadly applicable to the overall ecology of parallel applications migrating to the multi-core paradigm.