Nano-Scale On-Chip Irregular Network Analysis

Shrinking CMOS feature sizes and the integration of novel nanotechnologies onto silicon platforms are both likely to increase fabrication defects. As a result, on-chip networks become more and more irregular due to defects and it becomes more challenging to map computation and data onto the networks. One way to overcome this challenge is to configure the irregular network into a more conventional regular topology. In this paper we analyze nano-scale on-chip irregular networks to determine the regular topology most similar to a given irregular network. The results show that an irregular network is most similar to a tree. Further analysis is conducted based on configuring an irregular network into a tree structure to show whether there are opportunities to utilize links that are not included in the tree.