A 2.7 V mixed signal processor for CDMA/AMPS cellular phones

Author

Shi, Z.M. ; Salminen, O. ; Hsu, K. ; Wang, M. ; Maire, S. ; Vahe, J. ; Malo, E. ; Erkkila, E. ; Heikkila, J.M. ; Kaltiokallio, K.

Author_Institution

Mobile Phones Inc., San Diego, CA, USA

fYear

1999

fDate

1999

Firstpage

29

Lastpage

32

Abstract

This paper describes the design approach and test results of a monolithic mixed signal processor for use in dual-mode CDMA/AMPS (IS-95A) cellular phones. The processor interfaces between RF and digital baseband blocks. It comprises of a low jitter 9.8 MHz PLL, a high speed 4/8-bit CDMA/AMPS codec, channel filters, a 12-bit FM demodulator, a low power 13-bit voice codec and speech filters. The processor design is targeted for low power applications and fabricated in a low power 0.5 μm CMOS technology. The statistical test results measured from -30°C to +85°C with a standard process variation demonstrate that the system completely fulfils IS-98A CDMA handset performance specification

Keywords

CMOS integrated circuits; cellular radio; code division multiple access; demodulators; low-power electronics; mixed analogue-digital integrated circuits; speech codecs; telephone sets; -30 to 85 C; 0.5 micron; 2.7 V; 9.8 MHz; CDMA/AMPS cellular phones; FM demodulator; IS-98A CDMA handset performance specification; channel filters; dual-mode cellular phones; high speed codec; low jitter PLL; low power CMOS technology; low power applications; low power voice codec; monolithic mixed signal processor; speech filters; Baseband; CMOS technology; Cellular phones; Codecs; Filters; Multiaccess communication; Radio frequency; Signal design; Signal processing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 1999 IEEE

Conference_Location

Anaheim, CA

ISSN

1097-2633

Print_ISBN

0-7803-5604-7

Type

conf

DOI

10.1109/RFIC.1999.805233

Filename

805233