Dual-mode VLSI array for polynomial multiplication using residue arithmetic

A two-mode processing element for VLSI processor arrays is presented. It forms the core of a nine-element building block which attempts to overcome the communication bottleneck and to enhance the reliability of the systolic architecture. The potential of the proposed VLSI computing structure has been demonstrated by the implementation of a mapping algorithm for polynomial multiplication utilizing the residue arithmetic philosophy. It is concluded that the proposed architecture offers an attractive medium for implementing a wide spectrum of matrix-VLSI algorithms. The power of the modular configuration comes from the fact that the interconnection pattern is regular and the dual-mode switchable central processing element allows the structure to be reconfigured in accordance with the algorithm to be mapped on it, or vice versa