Title :
On hardware overhead in CMOS BIST designs
Author :
Kim, Kwanghyun ; Tront, Joseph G. ; Ha, Dong S.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The hardware overhead in CMOS BIST (built-in self-testing) designs are investigated. Various BIST components are implemented using CMOS and hardware overheads are assessed in terms of the number of transistors. Since the hardware overhead for each component is represented with a simple formula, it is very easy to estimate the hardware overhead in the early design process. The implementation of three components (built-in logic block observer, signature analysis register, and pseudorandom pattern generator) is described in detail
Keywords :
CMOS integrated circuits; automatic testing; integrated circuit testing; logic testing; CMOS BIST designs; built-in logic block observer; built-in self-testing; design process; hardware overhead; pseudorandom pattern generator; signature analysis register; Built-in self-test; CMOS technology; Circuit testing; Hardware; Logic testing; Performance evaluation; Process design; Registers; Silicon; Test pattern generators;
Conference_Titel :
Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE
Conference_Location :
Columbia, SC
DOI :
10.1109/SECON.1989.132474
