A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

Author

Kwanseo Park ; Woorham Bae ; Haram Ju ; Jinhyung Lee ; Gyu-Seob Jeong ; Yoonsoo Kim ; Deog-Kyoon Jeong

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

fYear

2015

fDate

24-27 May 2015

Firstpage

2389

Lastpage

2392

Abstract

A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm² and consumes 22.1 mW at the data rate of 10 Gb/s.

Keywords

CMOS integrated circuits; clocks; delay lock loops; jitter; phase locked loops; CMOS technology; DLL; PLL-based forwarded clock receiver; bit rate 10 Gbit/s; deskewing; hybrid PLL-based deskew; jitter filtering; power 22.1 mW; power consumption; ring-oscillator-based PLL; rms jitter; size 65 nm; Clocks; Jitter; Phase frequency detector; Phase locked loops; Receivers; Synchronization; Voltage-controlled oscillators; DLL; Forwarded clock receiver; hybrid; low jitter; ring PLL;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7169165

Filename

7169165