DocumentCode
3323900
Title
Parallel implementations of discrete relaxation technique on fixed size processor arrays
Author
Lin, Wei-Ming ; Prasanna, Viktor
Author_Institution
Dept. of EE-Systs., Univ. of Southern California, Los Angeles, CA, USA
fYear
1991
fDate
2-4 Sep 1991
Firstpage
184
Lastpage
198
Abstract
Discrete relaxation technique has been widely used in pattern recognition, artificial intelligence and computer vision. For the consistent labeling problem for labeling n objects with m labels, a parallel implementation based on a new sequential algorithm is shown. This non-partitioned parallel implementation runs in O (nm ) time using nm PE ´s. Two partitioned implementations are then proposed. In the first implementation, O (n 2m 2/ P ) time performance is achieved by using P PE ´s connected to a common bus, where P ⩽nm . An alternate linear array implementation is also proposed which runs in O ((nm /P +P )nm ) time. This achieves linear speedup when nm ⩾P 2
Keywords
artificial intelligence; computer vision; parallel processing; pattern recognition; O; artificial intelligence; computer vision; consistent labeling problem; discrete relaxation technique; fixed size processor arrays; linear array implementation; parallel implementations; partitioned implementations; pattern recognition; sequential algorithm; Artificial intelligence; Broadcasting; Computer vision; Digital images; Labeling; Layout; Partitioning algorithms; Pattern matching; Pattern recognition; Stereo vision;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Specific Array Processors, 1991. Proceedings of the International Conference on
Conference_Location
Barcelona
Print_ISBN
0-8186-9237-5
Type
conf
DOI
10.1109/ASAP.1991.238884
Filename
238884
Link To Document