Title :
A split transconductor high-speed SAR ADC
Author :
Muratore, Dante Gabriel ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution :
Dept. of Electr., Comput. & Biomed. Eng., Univ. of Pavia, Pavia, Italy
Abstract :
A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; FDSOI CMOS technology; high speed SAR ADC; optimal architecture; size 28 nm; split transconductor; Arrays; CMOS integrated circuits; Capacitance; Capacitors; Latches; Topology;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7169176
