Title :
Timing generator using dual delay-locked loop
Author :
Hwang, Chorng-Sii ; Chen, Ke-Han ; Tsao, Hen-Wai
Author_Institution :
Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan
fDate :
Oct. 24 2009-Nov. 1 2009
Abstract :
In this paper, the new architecture of a timing generator using dual delay-locked loop (DLL) is proposed. With the aid of coarse and fine tuning mechanisms, the timing generator can provide sub-gate resolution with precise close-loop control and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.35 ¿m 2P4M technology. The chip area occupies 1.36 mm2. It can interpolate the reference clock cycle with 80 divisions to obtain 45 ps resolution when running at 280 MHz. The DNL and INL are within -0.3~+0.6 and -0.8~+0.4 LSB, respectively.
Keywords :
closed loop systems; delay lock loops; digital-analogue conversion; pulse circuits; timing circuits; TSMC 2P4M technology; close loop control; coarse tuning; differential nonlinearity; dual delay locked loop; fine tuning; frequency 280 MHz; instantaneous switching capability; integral nonlinearity; reference clock cycle interpolation; size 1.36 mm; timing generator; Circuit optimization; Clocks; Delay; Logic testing; Nuclear power generation; Open loop systems; Pulse generation; Signal generators; Signal resolution; Timing;
Conference_Titel :
Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-3961-4
Electronic_ISBN :
1095-7863
DOI :
10.1109/NSSMIC.2009.5401573
