A modular systolic 2-D torus for the general knapsack problem

The authors propose a modular 2-D torus pipelined processing elements for solving the general knapsack problem of arbitrary size. Each cell has a fixed storage capacity α₀ independent of the particular knapsack problem to be solved. They study the vertical speed up defined as the speed up achieved upon the I-D torus, when the capacity of the knapsack goes to infinity; and its associated efficiency. The knapsack problem is a very important optimization problem because it has a wide range of applications and also appears as a suboptimization task of other optimization schemes. Its dependence graph lacks the regularity usually required for systolic implementation. Its shape namely depends on the set of weights to be included in the knapsack. Therefore the distribution of weights influences the speed up. Precisely they show that the minimum and maximum weights w_min and w_max define an upper bound for the possible vertical speed up: w_max/(w_max-w_min+2). α ₀ is also an upper bound of this speed up. They simulate a cell with a larger memory grouping cells g by g, where g=[w_max/α₀]. The torus always reaches a quarter of its upper bound with an efficiency of 1/(4*g)