Processor clustering for the design of optimal fixed-size systolic arrays

The authors have shown in their previous work that processor-clustering is a key operation in the design of problem-size independent systolic/wavefront arrays. Indeed, the processor clustering techniques (called passive-clustering and active-clustering) can not only be used to reduce the size of an array to a constant, but also to achieve the design objectives such as transforming inefficient arrays into efficient arrays, reducing the dimension of an array, and balancing local memory and external communication of processors in a systematic way, etc. They have shown that such an operation can be completely described in terms of a set of so-called clustering vectors. They derive explicit expressions for all possible clustering vectors. A simple and constructive procedure is given for the computation of these vectors. This makes processor clustering operations constructive and suitable for computer CAD software implementation. Moreover, they show that the concept and procedure described for the processor clustering can be used hierarchically at different levels of a design. This way, fixed-size arrays can be designed in a hierarchical and parameterized, semi-automatic way