A design method for on-line reconfigurable array processors

A design methodology for reconfigurable array processors is described which extends a known design method for non-redundant array architectures. Using self-checking processing elements, the systematic design of on-line reconfigurable arrays is feasible, which perform reconfiguration concurrently with data processing. Reconfiguration schemes suitable for one- and two-dimensional array processors are presented. Another scheme addresses arrays with high probability of dynamic faults while static faults cannot be neglected. Dynamic and static faults are treated differently to reduce hardware overhead. A systematic approach for reliability estimation based on a model including dynamic and static faults is discussed. The design method is applied to matrix-matrix-multiplication. Estimations of hardware overhead are given