Synthesizing systolic arrays: some recent developments

Methods for synthesizing systolic arrays from uniform DAGs are well understood. The idea is to extract from the original sequential algorithm a dependence graph where all incoming arcs to a given node come from a fixed-size neighborhood, so that dependencies are local. Space-time transformations are then used for scheduling the DAG (timing function) and mapping nodes onto physical processors (allocation function). Both linear and piece-wise linear mappings can be derived in a systematic way, and methods exist to optimize given criteria such as the execution time, the number of processors or the cell utilization. The authors survey three recent developments along the following lines: DAG uniformization and spacetime minimal arrays; mapping n-dimensional DAGs (n⩾3) onto linear arrays; and partitioning techniques for the efficient mapping of a computational DAG onto a fixed-size processor array