Design of NoC router with flow control mechanism for congestion avoidance

To achieve high performances at the application level in multiprocessor architecture MP-SoC, the NoC router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for flow control in order to avoid congestion in network on chip. This mechanism is used conjointly with an appropriate approach to manage flits buffering that allows dropping low important flits when the router is in a congestion state. The performances analysis of this router as well as it´s the hardware characteristics are studied and presented in this paper.