DocumentCode :
3324685
Title :
DPLL with hybrid ΔΣ phase/frequency detector
Author :
Syllaios, Ioannis L. ; Jensen, Henrik T.
Author_Institution :
Broadband & Connectivity Group, Broadcom Corp., Irvine, CA, USA
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
2569
Lastpage :
2572
Abstract :
Digital phase-locked loop (PLL) with dynamic hybrid Delta-Sigma (ΔΣ) phase/frequency detector (PFD). It combines the benefits of a traditional analog charge-pump-based PLL and a modern time-to-digital converter (TDC)-based all-digital PLL, namely, infinite phase-error detection resolution and all-digital control of a digitally controlled oscillator, respectively. An Lth-order ΔΣ analog-to-digital converter (ADC) implements an (L+1)-order ΔΣ PFD via closed-loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates multi-bit phase/frequency error digitization. A spur-free, wide bandwidth DPLL with a hybrid 2nd-order ΔΣ PFD that is based on a 1st-order continuous-time multi-bit ΔΣ ADC is presented in this paper. Low analog implementation complexity is achieved via digital noise-shaping requantization and noise cancellation.
Keywords :
analogue-digital conversion; delta-sigma modulation; digital phase locked loops; phase detectors; analog-digital converter; closed loop frequency detection; digital noise shaping requantization; digital phase locked loop; hybrid deta-sigma phase-frequency detector; hybrid second order delta-sigma PFD; multibit phase-frequency error digitization; noise cancellation; spur-free DPLL; widebandwidth DPLL; Detectors; Frequency synthesizers; Noise; Noise shaping; Phase frequency detector; Phase locked loops; Quantization (signal);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7169210
Filename :
7169210
Link To Document :
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