Power optimization design for probabilistic logic circuits

With CMOS technology approaching the nanometer scale, probabilistic design has received much attention from the research community. In this paper, we propose a power optimization methodology for probabilistic logic circuits with stochastic components. Inexactness in circuits allows the local reliability-power tradeoff of unreliable components, and provides us with design space for power optimization. The proposed approach aims to minimize the power cost of circuits under certain error rate constraints. We show that the proposed method outperforms other intuitive approaches by a factor of 2.5X, on average, in terms of power costs under a same target error rate.