A programmable DCO-based digital clock multiplier and divider

A programmable DCO-based digital clock multiplier and divider is presented in this paper. The multiplication ratio M and division ratio D can be programmed from 2 to 32, and 1 to 32, respectively. The proposed architecture uses a coarse tune circuit to reduce the lock time and a phase maintenance mechanism to overcome the process, voltage, and temperature (PVT) variations. With a new switching control scheme is employed in the digitally controlled oscillator (DCO), the clock generator achieves similar jitter performance as conventional MDLL. The frequency range of the input and output clock are 1 ~ 270 MHz and 15 ~ 400 MHz, respectively. This clock generator is implemented in TSMC 0.13-μm CMOS technology. The measured cycle-to-cycle timing jitter at 400 MHz is 8.4ps (rms) and 117 ps (pk-pk) with a power consumption of 24 mW at a 1.5-V power supply.