Topological symbolic simplification for analog design

Symbolically generated network functions for an analog integrated circuit are complicated in general. For this reason a variety of simplification methods have been proposed in the literature. In this work a novel topology-based symbolic simplification method is proposed, which is capable of generating a simplified symbolic network function together with a simplified small-signal circuit. The technique is developed by applying the recently proposed graph-pair decision diagram (GPDD) algorithm that generates a symbolic network function stored in a binary decision diagram (BDD). Two types of element elimination can directly be operated on such a GPDD data structure. The performance variation by eliminating each symbol from the original circuit is assessed by the means of two monitored response metrics (dc gain and phase margin). After sorting the performance loss, those circuit elements with less performance loss are eliminated, resulting in a reduced GPDD which is automatically a simplified network function. A simplified small-signal circuit is available simultaneously after reduction. Applications to two operational amplifier examples confirm the effectiveness of the proposed methodology.