Building standards based COTS multiprocessor computer systems for space around a high speed serial bus network

Discusses higher performance processing requirements where as many as a dozen RAD6000s would work together to perform payload processing and other onboard processing tasks on a satellite. This work led to an alternate subsystem architecture to the common parallel bus used to interconnect elements in a typical subsystem. After an comprehensive trade study, a multiplexed set of serial busses based on an emerging IEEE standard (IEEE 1394-1995) was chosen as the most cost effective and scalable architecture for future multiprocessor payloads. A radiation-hardened Application Specific Integrated Circuit (ASIC) was developed to implement a bridge to this interface from the RAD6000 and its support chip. This chip was fabricated, tested and demonstrated in two similar multiprocessor systems. This paper describes the trades that led to this chip, its features and performance. It describes the device drivers developed for running under the VxWorks operating system and the performance that was measured. The paper will describe a loosely coupled thirteen-processor system interconnected by these chips that was developed. It will describe how IEEE 1394´s updates being worked out in standards bodies this year may be applied to future space systems requiring both higher performance and more remote interconnections between processors such as the Power PC