Using the hardware/software co-design methodology to implement an embedded face recognition/verification system on an FPGA

An embedded face recognition/verification system has been implemented on an FPGA. The system recognizes/verifies the user by capturing his/her facial image via a digital image sensor and runs a series of DSP algorithms to reach the decision. It is embedded and small in size allowing it to suit a wide range of applications. It is based on an FPGA which offers high configurability in the design phase. The hardware/software codesign methodology was used which enabled optimizing the system to meet different design constraints including size, cost and power dissipation. A number of DSP algorithms were used or created to detect the face from a background, enhance the image and recognize the person. The principal component analysis algorithm was used for feature extraction.