DocumentCode
332586
Title
A BIST scheme for asynchronous logic
Author
Alves, Vladimir C. ; França, Felipe M G ; Granja, Edson P.
Author_Institution
COPPE Eletrica, Univ. Fed. do Rio de Janeiro, Brazil
fYear
1998
fDate
2-4 Dec 1998
Firstpage
27
Lastpage
32
Abstract
This work introduces a methodology to ease the implementation of BIST in asynchronous circuits. Scheduling by edge reversal (SER), a simple but powerful distributed synchronizer is used to implement a sequencer that allows testing the circuit at full speed. The methodology, which allows the detection of topological faults, is proved correct. Low hardware overhead and the absence of deadlocks are the main characteristics of the proposed methodology
Keywords
asynchronous circuits; built-in self test; fault diagnosis; integrated circuit testing; logic testing; scheduling; BIST scheme; asynchronous logic; distributed synchronizer; edge reversal; full speed testing; hardware overhead; topological faults; Asynchronous circuits; Built-in self-test; Circuit faults; Circuit testing; Clocks; Electrical fault detection; Hardware; Logic; Observability; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741575
Filename
741575
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