IDDQ test methodology and tradeoffs for scan/non-scan designs

I_DDQ techniques have been widely used at Intel over the past years to (a) successfully improve outgoing quality of the products by screening defects early in production testing, (b) eliminate or reduce burn in, and (c) improve overall fault grading. Functional (non-scan) I_DDQ testing has been implemented successfully on a number of products (i960(R), i386^TMEX, and MCS(R) micro-controllers). With more designs implementing scan, the capability to select, grade and implement scan-based I_DDQ vectors and the resulting contribution to the overall fault coverage can be complicated. Using this I_DDQ test methodology, we show how to (a) integrate test techniques into the design flow (b) eliminate the need for fault grading, (c) use scan/I_DDQ to improve fault coverage, and (d) determine the incremental non-scan and scan I_DDQ coverage impact on the full chip. This paper details the new test technique, methodology, flows, tradeoffs/benefits, implementation, and results for I_DDQ vector generation, grading, selection and testing of vectors for non-scan and scan-based designs. This technique allows user(s) the option of eliminating comprehensive fault grading resources, and uses existing or new Electronic Design Automation (EDA) tools to achieve desired quality levels prior to design completion, and production testing