DocumentCode :
3326018
Title :
An area reduced, speed optimized implementation of viterbi decoder
Author :
Karim, M.U. ; Khan, Muhammad Usman Karim ; Khawaja, Y.M.
Author_Institution :
Dept. of Comput. Syst. Eng., Univ. of Eng. & Technol., Peshawar, Pakistan
fYear :
2011
fDate :
11-13 July 2011
Firstpage :
93
Lastpage :
98
Abstract :
A fast implementation of the Viterbi decoder is discussed in this paper. It is shown that the proposed design is area efficient, reduces memory requirements and has a larger throughput then parallel Viterbi implementations. Techniques used to achieve these goals are retiming, pipelining and parallel to serial conversion which are implemented at the gate level. VLSI designs of constituent blocks of the decoder are shown and thorough analysis of the critical path delay of each decoder segment is deliberated which illustrates that the resulting design imposes minimum penalties in terms of clock speed and circuit area.
Keywords :
VLSI; Viterbi decoding; logic design; VLSI design; Viterbi decoder; critical path delay analysis; decoder circuit area; decoder clock speed; decoder segment; pipelining technique; retiming technique; serial conversion technique; very large scale integration; Decoding; Hardware; Silicon; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Networks and Information Technology (ICCNIT), 2011 International Conference on
Conference_Location :
Abbottabad
ISSN :
2223-6317
Print_ISBN :
978-1-61284-940-9
Type :
conf
DOI :
10.1109/ICCNIT.2011.6020914
Filename :
6020914
Link To Document :
بازگشت