Title :
Comprehensive interconnect BIST methodology for virtual socket interface
Author :
ChauChin Su ; Chen, Yue-Tsung
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
Comprehensive interconnect BIST achieves 100% fault coverage on net faults and driver faults without any prerequisitive assumption on the connection configuration and the fault-free and faulty behavior of the interconnects. Guidelines are derived and structure maps are proposed to achieve the goal
Keywords :
application specific integrated circuits; boundary scan testing; built-in self test; fault diagnosis; integrated circuit interconnections; integrated circuit testing; standardisation; connection configuration; driver faults; fault coverage; interconnect BIST methodology; net faults; structure maps; virtual socket interface; Automatic testing; Built-in self-test; Councils; Guidelines; Hardware; Intellectual property; Logic testing; Sockets; Standardization; Virtual colonoscopy;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741622
