A diagnosis method for interconnects in SRAM based FPGAs

Author

Yu, Yinlei ; Xu, Jian ; Huang, Wei Kang ; Lombardi, Fabrizio

Author_Institution

Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

1998

fDate

2-4 Dec 1998

Firstpage

278

Lastpage

282

Abstract

This paper presents a five-step programming method to diagnose faults in FPGA interconnection resources. A single and a multiple fault model are given. The accuracy of fault location is a single segment for a segment stuck-at fault or a segment open fault, a segment pair or terminal pair for bridge fault or switch stuck-off fault under the single fault assumption. Similar accuracy can be achieved under the multiple fault assumption

Keywords

PLD programming; fault diagnosis; fault location; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; random-access storage; FPGA interconnects; SRAM based FPGAs; Xilinx FPGAs; bridge fault; diagnosis method; fault location; five-step programming method; interconnection resources; multiple fault model; segment open fault; segment stuck-at fault; single fault model; switch stuck-off fault; Bridges; Circuit faults; Fault detection; Fault diagnosis; Fault location; Field programmable gate arrays; Integrated circuit interconnections; Logic programming; Random access memory; Switches; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

ISSN

1081-7735

Print_ISBN

0-8186-8277-9

Type

conf

DOI

10.1109/ATS.1998.741625

Filename

741625