Title :
Observation time reduction for IDDQ testing of bridging faults in sequential circuits
Author :
Higami, Yoshinobu ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution :
Fac. of Eng., Ehime Univ., Matsuyama, Japan
Abstract :
One of the major unsolved and ignored but significant problems is the reduction of the long testing time for IDDQ testing of CMOS circuits. Since IDDQ must be observed after dynamic current disappears, testing time is much longer than logic testing. This paper presents a method to reduce the observation time for IDDQ testing. The proposed method is a static method which focuses on selection of vectors to be observed instead of removing vectors. Experimental results are presented to demonstrate the effectiveness of the proposed method
Keywords :
CMOS logic circuits; automatic testing; integrated circuit testing; logic testing; sequential circuits; CMOS circuits; IDDQ testing; bridging faults; observation time reduction; sequential circuits; static method; vectors selection; CMOS logic circuits; Circuit faults; Circuit testing; Clocks; Computational modeling; Electrical fault detection; Fault detection; Logic testing; Sequential analysis; Sequential circuits;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741631
