Co-simulation platform based on systemc for multiprocessor system on chip architecture exploration

Currently multiprocessor embedded systems are the principal vectors of semiconductor industry. Modelling, validating and analyzing a system performances impose the evolution of the traditional simulation techniques. In this paper we define the methodology we used in constructing the STARSoC co-simulation environment. This platform aims to explore at higher levels of abstractions a multiprocessors system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. Our purpose is to develop a complete design space exploration tool. In order to assist the system designer in finding the best MPSoC solution depending on the proposed application. We used SystemC language for modelling and simulating at higher level of abstraction in order to speed up the simulation time, compared to the Register Transfer Level (RTL) simulation time. The platform includes models for OpenRISC ISSs, wishbone Bus Functional Model (BFM) and memory models. The simulation is based on different high abstraction levels.