Title :
Vector restoration using accelerated validation and refinement
Author :
Bommu, Surendra K. ; Chakradhar, Srimat T. ; Doreswamy, Kiran B.
Author_Institution :
Comput. & Commun. Res. Labs., NEC Res. Inst., Princeton, NJ, USA
Abstract :
Given a test sequence and a list of faults detected by the sequence, vector restoration techniques extract a minimal subsequence that detects a chosen subset of faults. Vector restoration techniques are useful in static compaction of test sequences and in fault diagnosis. We propose a new vector restoration technique that is a significant improvement over the state of the art in several ways: (1) a sequence of length n can be restored with only O(nlog2n) simulations while known approaches require simulation of O(n2) vectors; (2) a two-step restoration process is used that makes vector restoration practical for large designs; and (3) the restoration process for several faults is overlapped to provide significant acceleration in vector restoration. Our new ideas can be used to improve run-times of known static compaction and fault diagnosis methods. We integrated the proposed vector restoration technique into a static test sequence compaction system. Our experiments show that the new restoration technique, as compared to known techniques, is for (1) about 2 times faster for the ISCAS benchmark circuits, and for (2) 3 to 5 times faster on large, industrial designs. Using the new restoration technique, we successfully processed large industrial designs that could not be handled by earlier techniques in 2 CPU days
Keywords :
automatic test pattern generation; binary sequences; circuit analysis computing; fault diagnosis; logic testing; sequential circuits; vectors; ATPG; accelerated refinement; accelerated validation; fault diagnosis; large industrial designs; minimal subsequence extraction; overlapped process; static compaction; static test sequence compaction system; test sequences; two-step restoration process; vector restoration techniques; Acceleration; Benchmark testing; Circuit faults; Circuit testing; Compaction; Fault detection; Fault diagnosis; Process design; Runtime; System testing;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741657