Implementing fast recovery for register alias table in out-of-order processors

Register renaming is an indispensable technique to cope with false data dependencies in out-of-order processors. The critical component for performing register renaming is a register alias table (RAT), which maintains the mappings between architecture and physical registers. Unfortunately, a potential misprediction may seriously slower the processor execution, because new instructions are not allowed to be renamed until the RAT has been restored to the previous correct status. Therefore, a fast RAT recovery is necessary to sustain high performance. As instruction windows size increases, the traditional recovery mechanisms such as using retirement map table and history buffer become too slow. In order to instantly restore RAT from a misprediction, the embedded checkpoint method is introduced but too costly due to creating a large number of checkpoints. In this paper, we propose a selective checkpoint policy which is based on branch confidence and decides when to assign a new checkpoint. Experimental results show that for a 2048-entry large instruction window, our proposal only uses 8 checkpoints to implement fast RAT recovery, reducing the misprediction overhead to just 3% of the ideal model.