Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance

We report a study of power supply reduction to near-threshold for an 8-transistor CNTFET SRAM cell. Voltage at near-threshold has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with non-semiconductor CNTs. In this study we investigate how to enhance SRAM performance by means of two techniques: Gated Power Supply and Word-line Boosting. Using the gated power supply technique, power saving is over 5X, while the average delay is increased by 3.5X as compared to 0.9V Vdd. On the other hand, word-line boosting technique (where Read and write word lines are boosted with additional 100mV) helps to improve write and read delays that are faster by 3.8X and 1.7X, respectively at Vdd=0.4V. Lowest Energy delay product (EDP) for gated power supply and word-line boosting is at 0.5V and 0.4V, respectively. EDP compared to nominal Vdd of 0.9V is lowered by 38% and 56.9% respectively for the mentioned techniques.