2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents

Leakage power that is consumed by gigascale clock distribution networks is an important challenge in modern synchronous integrated circuits with billions of deeply-scaled transistors. A novel dual-threshold-voltage repeater circuit with split inputs and outputs is employed for achieving enhanced power efficiency in clock distribution networks in this paper. With the new repeaters, the mean of the statistical leakage power consumption distribution is reduced by up to 39.6% without increasing the layout area, active power consumption, clock skew, and clock period as compared to a conventional clock distribution network with standard static CMOS inverter based repeaters in a TSMC 65nm CMOS technology.