Surface-gate SIT with high breakdown voltage for low power applications

A static-induction transistor (SIT) with surface-gate structure design method through solving epi-layer parameter and source breakdown voltage (BV_GSO) as sally port is described. A high performance SIT is manufactured and tested in this paper. Based on the previous experiences and theory, a proper epi-layer is chosen. Then targeting to the design goal, other structure parameters are deduced by ways of theoretical formulae successively. The layout design are also described to possess adequate drain current, especially the channel width and unit amount. As semiconductor technology had been the main problem which restricted the development of surface-gate SIT, the key fabrication processes are also presented. Experimental results have good agreement with the values we expected. Which means the method we use is credible and can be a guidance for further SIT design and will push the research of surface-gate SIT forward.