The 5ns peaking time transimpedance front end amplifier for the silicon pixel detector in the NA62 Gigatracker

We present the design and test results of a front-end prototype circuit developed in 130 nm CMOS technology for the readout of the Gigatracker pixel detector experiment in NA62 at CERN. The main challenges for the front end amplifier are very high signal hit rate (dead time less than 100 ns, average signal rate 100 kHz) and 100 ps timing resolution combined with the level of affordable power consumption (< 2 W/cm²) and noise (< 200 e^- ENC). The predicted ENC levels for the nominal detector capacitance of 250 fF and maximum leakage current of the order of 20 nA are below 200 e^-. The overall power consumed by the analogue and digital part of the pixel cell is in the order of 130 ¿W. The optimization of the design as well as test results of the prototype front end chip are evaluated and discussed.