DocumentCode :
3326604
Title :
A 128 channel 290 GMACs/W machine learning based co-processor for intention decoding in brain machine interfaces
Author :
Yi Chen ; Enyi Yao ; Basu, Arindam
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
3004
Lastpage :
3007
Abstract :
A machine learning co-processor in 0.35μm CMOS for motor intention decoding in the brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm, time delayed sample based feature dimension enhancement, low-power analog processing and massive parallelism, it achieves an energy efficiency of 290 GMACs/W at a classification rate of 50 Hz. A portable external unit based on the proposed co-processor is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3%. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels.
Keywords :
CMOS integrated circuits; brain-computer interfaces; coprocessors; decoding; delay circuits; encoding; learning (artificial intelligence); CMOS; brain machine interfaces; low-power analog processing; machine learning based co-processor; massive parallelism; motor intention decoding; size 0.35 mum; time delayed sample based feature dimension enhancement; Accuracy; Brain-computer interfaces; Decoding; Mirrors; Neurons; Radiation detectors; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7169319
Filename :
7169319
Link To Document :
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